In current semiconductor industry, integrate circuit (IC) products are classified into three major types including analog circuit, digital circuit, and digital/analog hybrid circuit. Memory device is an important type of device in digital circuit. In recent years, flash memory, as a memory device, has been developed rapidly. A main feature of the flash memory is capability of long-term information storage without electric power. Flash memory also has some advantages including high degree of integration, fast write/access speed, and easy erase and rewrite operations. Therefore, flash memory has been widely applied to various fields such as microcomputer and automatic control.
FIG. 1 depicts a cross section of an existing flash memory storage unit (or flash memory cell). The cell includes a substrate 10, a tunneling oxide layer 11 on the surface of the substrate 10, and a floating gate 12 on the surface of the tunneling oxide layer 11. An opening is formed in the tunneling oxide layer 11 and in the floating gate 12 to expose the substrate 10. The cell further includes sidewall spacers 13 on the top surface of the floating gate 12 and covering sidewalls of the opening. The cell further includes a source line layer 14 on the surface of the substrate 10 at the bottom of opening. The source line layer 14 covers a portion of the surface of the sidewall spacers 13, and the surface of the source line layer 14 is not higher than the top of the sidewall spacers 13. Furthermore, the cell includes a word line layer 15 located outside the sidewall spacers 13, the source line layer 14, and the floating gate 12. The word line layer 15 is electrically isolated from the floating gate 12 by an insulating layer 16.
Floating gates of multiple flash memory cells formed on the same substrate need to be electrically isolated by isolation structures. FIG. 2 depicts an isolation structure for isolating a floating gate of a flash memory cell. The flash memory cell includes a substrate 20 having a floating gate region 21 and an isolation region 22, a tunneling oxide layer 25 on the surface of the substrate 20 at the floating gate region 21, and a floating gate layer 23 on the surface of the tunneling oxide layer 25. The flash memory cell further includes an isolation structure 24 in the substrate 20 at the isolation region 22. The isolation structure 24 includes a first region A and a second region B. The first region A and the second region B are adjacent to each other. A source line layer, such as the source line layer 14 as shown in FIG. 1, stretches across the first region A of the isolation structure 24. A portion of the floating gate layer 23 corresponding to the second region B of the isolation structure 24 is removed by etching in a subsequent process.
However, the floating gate layer and the isolation structure formed by existing technology often have poor morphology, so the performance of the subsequently-formed flash memory cell is often unstable. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.